1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a data input/output circuit of a semiconductor memory device, and an operation method thereof.
2. Description of the Related Art
In general, when a semiconductor memory device has even one defective cell amongst many thousands of cells, it is treated as a failed product. However, discarding the entire memory device as a failed product due to failure of only a few cells is not efficient in terms of yield.
At the present time, a defective cell is replaced with a replacement cell that is designated in advance so that the memory device can be salvaged, resulting in an improvement in yield. In the prior art, during a data input operation in which input data and an external address are inputted, it is determined whether the external address is a main address or a repair address through an address comparison circuit, and the input data is transmitted to and stored in a main buffer or a repair buffer based on a determination result.
In the aforementioned data input method, it is necessary to further ensure an operation time margin for simultaneously inputting data to the main buffer and the repair buffer and storing the data therein due to the time required for the address comparison operation.